kfm2g16q2m-deb8 Samsung Semiconductor, Inc., kfm2g16q2m-deb8 Datasheet - Page 103

• Manufacturer Part Number: kfm2g16q2m-deb8
• Description: 2gb Muxonenand M-die
• Manufacturer: Samsung Semiconductor, Inc.

3.9.1
Read Mode
3.9.2 Continuous Linear Burst Read Operation During Synchronous
Burst Block Read Mode
MuxOneNAND2G(KFM2G16Q2M-DEBx)
MuxOneNAND4G(KFN4G16Q2M-DEBx)
MuxOneNAND8G(KFK8G16Q2M-DEBx)
In a Synchronous Burst Block Read, data is output with respect to a clock input.
MuxOneNAND is capable of a continuous linear burst operation within one block size and a fixed-length linear burst operation of a
preset length.
Note that only INT pin is valid indicator signal for continuous linear burst read operation but both INT pin and bit are valid for a fixed-
length linear burst operation.
Same as the normal burst mode, the initial word will be output asynchronously, regardless of BRWL While the following words will be
determined by BRWL value.
The latency is determined by the host based on the BRWL bit setting in the System Configuration 1 Register. The default BRWL is 4
latency cycles. At clock frequencies of 40MHz or lower, latency cycles can be reduced to 3, at frequency range from 40MHz to
66MHz, latency cycle should be over 4. And at 83MHz frequency, BRWL should be set to 6. BRWL can be set up to 7 latency cycles.
The BRWL registers can be read during a burst read mode by using the AVD signal with an address.
First Clock Cycle
The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the
system by pulsing high. If the device is accessed synchronously while it is set to Asynchronous Read Mode, the first data can still be
read out.
Subsequent Clock Cycles
Subsequent words are output (Burst Access Time from Valid Clock to Output) tBA after the rising edge of each successive clock
cycle, which automatically increments the internal address counter.
Terminating Synchronous Burst Block Read
The device will continue to output sequential burst data until the system resets (Cold/Warm/Hot Reset), wrapping around until it
reaches the designated address (see Section 3.9.1 for burst address sequence). Asserting WE low is prohibited during Synchronous
Burst Block Read operation.
Burst Address Sequence During Synchronous Burst Block
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