stac9752xxtaeb2xr Integrated Device Technology, stac9752xxtaeb2xr Datasheet - Page 80

• Manufacturer Part Number: stac9752xxtaeb2xr
• Description: Two-channel, 20-bit, Ac ?97 2.3 Codecs With Microphone And Jack Sensing
• Manufacturer: Integrated Device Technology

9. LOW POWER MODES
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
The STAC9752/9753 is capable of operating at reduced power when no activity is required. The
state of power down is controlled by the Powerdown Register (26h). There are 7 commands of sep-
arate power down. The power down options are listed in Table 27. The first three bits, PR[2:0], can
be used individually or in combination with each other, and control power distribution to the ADCs,
DACs and Mixer. The last analog power control bit, PR3, affects analog bias and reference voltages,
and can only be used in combination with PR0, PR1, and PR2. PR3 essentially removes power from
all analog sections of the CODEC, and is generally only asserted when the CODEC will not be
needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only. PR2 and PR3 do not
need to be “set” before a PR4, but PR0 and PR1 should be “set” before PR4. PR5 disables the DSP
clock and does not require an external cold reset for recovery. PR6 disables the headphone driver
amplifier for additional analog power saving.
The Figure 22 illustrates one example procedure to do a complete powerdown of STAC9752/9753.
From normal operation, sequential writes to the Powerdown Register are performed to power down
STAC9752/9753 a section at a time. After everything has been shut off, a final write (of PR4) can be
executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding
their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line,
issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9752/9753 can
also be woken up with a cold reset. A cold reset will reset all of the registers to their default states
(Paged Registers are semi-exempt). When a section is powered back on, the Powerdown Control/
Status register (index 26h) should be read to verify that the section is ready (stable) before attempt-
ing any operation that requires it.
Normal
GRP Bits
Figure 22. Example of STAC9752/9753 Powerdown/Powerup flow
PR0=0 & ADC=1
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR0=1
Ready =1
ADCs off PR0
PCM_In ADCs & Input Mux Powerdown
PCM_Out DACs Powerdown
Analog Mixer powerdown (VREF still on)
Analog Mixer powerdown (VREF off)
Digital Interface (AC-Link) powerdown (BIT_CLK forced low)
Digital Clock disable, BIT_CLK still on
Powerdown HEADPHONE_OUT
PR1=0 & DAC=1
PR1=1
DACs off PR1
Default
Table 27. Low Power Modes
80
PR2=0 & ANL=1
PR2=1
PR2 or PR3
Analog off
Function
Cold Reset
PR4=1
STAC9752/9753
Digital I/F off
Warm Reset
PR4
AC-Link
Shut off
REV 3.3 1206