stac9752xxtaeb2xr Integrated Device Technology, stac9752xxtaeb2xr Datasheet - Page 27

• Manufacturer Part Number: stac9752xxtaeb2xr
• Description: Two-channel, 20-bit, Ac ?97 2.3 Codecs With Microphone And Jack Sensing
• Manufacturer: Integrated Device Technology

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
4.6.
4.6.1.
4.6.2.
AC-Link Power Management
Powering down the AC-Link
The AC-Link signals can be placed in a low power mode. When the AC‘97’s Powerdown Register
(26h) is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and
held at a logic low voltage level. After signaling a reset to AC‘97, the AC‘97 Controller should not
attempt to play or capture audio data until it has sampled a CODEC Ready indication from AC‘97.
BIT_CLK and SDATA_IN are transitioned low immediately following decode of the write to the Pow-
erdown Register (26h) with PR4. When the AC‘97 Controller driver is at the point where it is ready to
program the AC-Link into its low power mode, slots 1 and 2 are assumed to be the only valid stream
in the audio output frame.
After programming the AC‘97 device to this low power, halted mode, the AC‘97 Controller is required
to drive and keep SYNC and SDATA_OUT low.
Once the AC‘97 CODEC has been instructed to halt BIT_CLK, a special “wake-up” protocol must be
used to bring the AC-Link to the active mode since normal audio output and input frames can not be
communicated in the absence of BIT_CLK.
Waking up the AC-Link
There are two methods for bringing the AC-Link out of a low power, halted mode. Regardless of the
method, it is the AC‘97 Controller that performs the wake-up task.
4.6.2.1.
The AC-Link protocol provides for a “Cold AC‘97 Reset”, and a “Warm AC‘97 Reset”. The current
powerdown state ultimately dictates which form of AC‘97 reset is appropriate. Unless a “cold” or
“register” reset (a write to the Reset Register) is performed, wherein the AC‘97 registers are initial-
ized to their default values, registers are required to keep state during all powerdown modes.
Once powered down, re-activation of the AC-Link via re-assertion of the SYNC signal must not occur
for a minimum of four audio frame times following the frame in which the powerdown was triggered.
When AC-Link powers up, the CODEC indicates readiness via the CODEC Ready bit (input slot 0,
bit 15).
SDATA_OUT
SDATA_IN
BIT_CLK
Note: BIT_CLK not to scale
SYNC
Controller Initiates Wake-up
Figure 13. STAC9752/9753 Powerdown Timing
slot 2
frame
slot 2
frame
p e r
p e r
TAG
TAG
27
Write to
0x20
DATA
PR4
STAC9752/9753
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