stac9752xxtaeb2xr Integrated Device Technology, stac9752xxtaeb2xr Datasheet - Page 58

• Manufacturer Part Number: stac9752xxtaeb2xr
• Description: Two-channel, 20-bit, Ac ?97 2.3 Codecs With Microphone And Jack Sensing
• Manufacturer: Integrated Device Technology

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.1.18.
Bit(s) Reset Value
10:4
Bit(s)
3:0
11
15
14
13
12
11
10
9
EAPD
D15
D7
Powerdown Ctrl/Stat (26h)
Default: 000Fh
Reset Value
0
0
0
0
0
0
0
0
0
0
D14
PR6
D6
Read / Write
Read / Write
Read Only
RESERVED
Access
Name
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR5
D13
D5
RESERVED Bits not used, should read back 0
PG3:PG0
Name
I0
1 = Forces EAPD pad to Vdd
0 = Forces EAPD pad to GND
0 = Headphone Amp powered up
1 = Headphone Amp powered down
0 = Digital Clk active
1 = Digital Clk disable.
0 = digital active
1 = Powerdown: PLL, AC-Link, Xtal oscillator ;
0 = VREF and VREFOUT are active
1 = VREF and VREFOUT are powered down, and PR2 is asserted in
analog block
0 = analog active
1 = all signal path analog is powered down
0 = DAC powered up
1 = DAC powered down
PR4
D12
58
D4
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
The driver should not un-mask the interrupt unless ensured by the
AC ‘97 controller that no conflict is possible with modem slot 12 -
GPI functionality. Some AC’97 2.2 compliant controllers will not
likely support audio CODEC interrupt infrastructure. In either case,
S/W should poll the interrupt status after initiating a sense cycle
and wait for Sense Cycle Max Delay to determine if an interrupting
event has occurred.
Page Selector
0h = Vendor Specific
1h = Page ID 01 (See Section 8.4 for additional information on the
Paging Registers)
Fh = Reserved Pages
This register is used to select a descriptor of 16 word pages
between registers 60h to 6Fh. Value 0h is used to select vendor
specific space to maintain compatibility with AC’97 2.2 vendor
specific registers.
System S/W determines implemented pages by writing the page
number and reading the value back. All implemented pages must
be consecutive. (i.e., page 2h cannot be implemented without page
1h).
These registers are NOT reset on RESET#.
PR3
REF
D11
D3
Description
STAC9752/9753
Description
D10
PR2
ANL
D2
DAC
PR1
D9
D1
REV 3.3 1206
ADC
PR0
D8
D0