stac9752xxtaeb2xr Integrated Device Technology, stac9752xxtaeb2xr Datasheet - Page 72

• Manufacturer Part Number: stac9752xxtaeb2xr
• Description: Two-channel, 20-bit, Ac ?97 2.3 Codecs With Microphone And Jack Sensing
• Manufacturer: Integrated Device Technology

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.4.5.
Bit(s) Reset Value
14-11
9-5
15
10
D15
DL2
G4
D7
Function Information (68h
Register 24h must be set to Page 01h to access this register.
Default: 00xxh, see table 22: page73.
0
0
D14
DL1
G3
D6
DL4:DL0
G3:G0
Name
INV
G4
D13
DL0
G2
D5
Gain Sign Bit: The CODEC updates this bit with the sign of the gain value
present in G[3:0]. The BIOS updates this to take into consideration external
amplifiers or other external logic when relevant.
G[4] indicates whether the value is a gain or attenuation.
Gain in the G4 bit is in terms of dB.
This bit is Read/Write and is only reset on POR and not by RESET#.
Gain Bits: The CODEC updates these bits with the gain value (db relative to
level-out) in 1.5dBV increments. The BIOS updates these to take into
consideration external amplifiers or other external logic when relevant.
G[0:3] indicates the magnitude of the gain. G[4] indicates whether the value is a
gain or attenuation.
For Gain/Attenuation settings, see Table 23: page73.
These bits are read/write and are not reset on RESET#.
Inversion bit: Indicates that the CODEC presents a 180 degree phase shift to the
signal.
0h - No inversion reported
1h - Inverted
This bit is read/write and is not reset on RESET#.
BIOS should invert for each inverting gain stage.
Buffer delays: CODEC will provide number a delay measurement for the input
and output channels. Software will use this value to accurately calculate audio
stream position with respect to what is been reproduced or recorded. These
values are in 20.83 s (1/48000 second) units.
For output channels, this timing is from the end of AC Link frame in which the
sample is provided, until the time the analog signal appears at the output pin. For
input streams, this is from when the analog signal is presented at the pin until the
representative sample is provided on the AC Link.
Analog in and out paths are not considered as part of this delay.
The measurement is a “typical” measurement, at a 48 KHz sample rate, with
minimal in-CODEC processing (i.e., 3D effects are turned off.)
These bits are read/write and are not reset on RESET#.
The default value is the delay internal to the CODEC. The BIOS may add to this
value the known delays external to the CODEC, such as for an external
amplifier.
1Fh - reserved
00h - Information not provided
01h…1Eh - Buffer delay in 20.83 s units
Page 01h
D12
72
G1
D4
IV
)
D11
G0
D3
Description
RESERVED
STAC9752/9753
D10
INV
D2
DL4
D9
D1
REV 3.3 1206
DL3
FIP
D8
D0