stac9752xxtaeb2xr Integrated Device Technology, stac9752xxtaeb2xr Datasheet - Page 23

• Manufacturer Part Number: stac9752xxtaeb2xr
• Description: Two-channel, 20-bit, Ac ?97 2.3 Codecs With Microphone And Jack Sensing
• Manufacturer: Integrated Device Technology

4.
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
CONTROLLER, CODEC AND AC-LINK
4.1.
4.2.
AC-Link Physical Interface
Controller to Single CODEC
This section describes the physical and high-level functional aspects of the AC‘97 Controller to
CODEC interface, referred to as AC-Link.
The STAC9752/9753 communicates with its companion Digital Controller via the AC-Link digital
serial interface. AC-Link has been defined to support connections between a single Controller and
up to four CODECs. All digital audio, modem and handset data streams, as well as all control (com-
mand/status) information are communicated over this serial interconnect, which consists of a clock
(BIT_CLK), frame synchronization (SYNC), serial data in (SDATA_IN), serial data out
(SDATA_OUT) and a reset (RESET#).
The simplest and most common AC‘97 system configuration is a point-to-point AC-Link connection
between Controller and the STAC9752/9753, as illustrated in Figure 11.
A primary CODEC may act as either a source or a consumer of the bit clock (BIT_CLK), depending
on the configuration.
While RESET# is asserted, if a clock is present at the BIT_CLK pin for at least five cycles before
RESET# is de-asserted, then the CODEC is a consumer of BIT_CLK, and must not drive BIT_CLK
when RESET# is de-asserted. The clock is being provided by other than the primary CODEC, for
instance by the controller or an independent clock chip. In this case the primary CODEC must act as
a consumer of the BIT_CLK signal as if it were a secondary CODEC.
This clock source detection must be done each time the RESET# line is asserted. In the case of a
warm reset, where the clock is halted but RESET# is not asserted, the CODEC must remember the
clock source, and not begin generating the clock on the assertion of SYNC, if the CODEC had previ-
ously determined that it was a consumer of BIT_CLK.
Digital DC'97
Controller
Figure 11. AC-Link to its Companion Controller
SDATA_OUT
SDATA_IN
BIT_CLK
RESET#
SYNC
23
AC'97 Codec
XTAL_IN
XTAL_OUT
STAC9752/9753
REV 3.3 1206