stac9752xxtaeb2xr Integrated Device Technology, stac9752xxtaeb2xr Datasheet - Page 78

• Manufacturer Part Number: stac9752xxtaeb2xr
• Description: Two-channel, 20-bit, Ac ?97 2.3 Codecs With Microphone And Jack Sensing
• Manufacturer: Integrated Device Technology

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.4.12.
Bit(s) Reset Value
14:12
Bit(s) Reset Value
10:3
15:1
15
11
2
1
0
0
D15
D7
High Pass Filter Bypass (78h)
To unlock Register 78h, write 0xABBA to Register 76h.
Default: 0000h
0
0
1
0
0
0
0
0
0
D14
D6
EAPD_OEN
GPIOSLT12
ADC HPF BYP
GPIOACC
Reserved
Reserved
RESERVED
INTDIS
Name
EAPD
Name
D13
D5
EAPD data Enable
EAPD data is output on the EAPD pin when bit D11 = 1
EAPD data is input on the EAPD pin when bit D11 = 0
Bits not used, should read back 0
EAPD Pin Enable
0 = EAPD configured as input pin
1 = EAPD configured as output pin
Bits not used, should read back 0
Interrupt disable option.
Interrupts cleared by writing a 1 to I4 (Reg24h:D15)
0 = Will clear both SENSE and GPIO interrupts
1 = Will only clear SENSE interrupts. GPIO interrupts will have to be cleared in
Reg54h.
GPIO ACCESS
0 = ACLINK access from GPIO Pads
1 = ACLINK access from GPIO Register 54h
0 = GPIO0/1 access via Reg 54h when GPIO is set as an output, for input, Slot
12 data will be 0h.
1 = GPIO0/1 access via Slot 12 when GPIO is set as an output, for inputs,
Reg54h will not be updated.
This can only be used if a modem CODEC is not present in the system and using
Slot 12.
Bits not used, should read back 0
0 = ADC High Pass Filter active, (Normal operation)
1 = ADC High Pass Filter Bypass
RESERVED
D12
D4
78
RESERVED
D11
D3
Description
Description
D10
STAC9752/9753
D2
D9
D1
ADC HPF BYP
REV 3.3 1206
D8
D0