stac9752xxtaeb2xr Integrated Device Technology, stac9752xxtaeb2xr Datasheet - Page 2

• Manufacturer Part Number: stac9752xxtaeb2xr
• Description: Two-channel, 20-bit, Ac ?97 2.3 Codecs With Microphone And Jack Sensing
• Manufacturer: Integrated Device Technology

TABLE OF CONTENTS
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
1. PRODUCT BRIEF ...................................................................................................................... 7
2. CHARACTERISTICS AND SPECIFICATIONS .......................................................................10
3. TYPICAL CONNECTION DIAGRAM .......................................................................................20
4. CONTROLLER, CODEC AND AC-LINK .................................................................................23
5. AC-LINK DIGITAL INTERFACE ..............................................................................................29
1.1. Description ........................................................................................................................................ 7
1.2. STAC9752/9753 Block Diagram ........................................................................................................ 8
1.3. Key Specifications ............................................................................................................................. 8
1.4. Related Materials .............................................................................................................................. 9
1.5. Additional Support ............................................................................................................................. 9
2.1. Electrical Specifications ................................................................................................................... 10
2.2. AC Timing Characteristics ............................................................................................................... 16
3.1. Slit Independent Power Supply Operation ...................................................................................... 21
4.1. AC-Link Physical Interface .............................................................................................................. 23
4.2. Controller to Single CODEC ............................................................................................................ 23
4.3. Controller to Multiple CODECs ........................................................................................................ 25
4.4. Clocking for Multiple CODEC Implementations ............................................................................... 26
4.5. STAC9752/9753 as a Primary CODEC ........................................................................................... 26
4.6. AC-Link Power Management ........................................................................................................... 27
5.1. Overview ......................................................................................................................................... 29
5.2. AC-Link Serial Interface Protocol .................................................................................................... 30
5.3. AC-Link Output Frame (SDATA_OUT) ............................................................................................ 32
2.1.1. Absolute Maximum Ratings ............................................................................................... 10
2.1.2. Recommended Operation Conditions .............................................................................. 10
2.1.3. Power Consumption ......................................................................................................... 11
2.1.4. AC-Link Static Digital Specifications ................................................................................. 12
2.1.5. STAC9752 5 V Analog Performance Characteristics ....................................................... 12
2.1.6. STAC9753 3.3V Analog Performance Characteristics .....................................................14
2.2.1. Cold Reset ......................................................................................................................... 16
2.2.2. Warm Reset ....................................................................................................................... 16
2.2.3. Clocks ................................................................................................................................ 17
2.2.4. STAC9752/9753 Crystal Elimination Circuit and Clock Frequencies ................................17
2.2.5. Data Setup and Hold ........................................................................................................ 18
2.2.6. Signal Rise and Fall Times ............................................................................................... 18
2.2.7. AC-Link Low Power Mode Timing .................................................................................... 19
2.2.8. ATE Test Mode ................................................................................................................. 19
4.3.1. Primary CODEC Addressing ............................................................................................. 25
4.3.2. Secondary CODEC Addressing ........................................................................................ 25
4.3.3. CODEC ID Strapping ......................................................................................................... 26
4.5.1. STAC9752/9753 as a Secondary CODEC ........................................................................ 26
4.6.1. Powering down the AC-Link .............................................................................................. 27
4.6.2. Waking up the AC-Link ...................................................................................................... 27
4.6.3. CODEC Reset ................................................................................................................... 28
5.2.1. AC-Link Variable Sample Rate Operation ......................................................................... 30
5.2.2. Variable Sample Rate Signaling Protocol .......................................................................... 30
5.2.3. Primary and Secondary CODEC Register Addressing ...................................................... 32
5.3.1. Slot 0: TAG / CODEC ID ................................................................................................... 34
5.3.2. Slot 1: Command Address Port ......................................................................................... 34
5.3.3. Slot 2: Command Data Port ............................................................................................... 35
5.3.4. Slot 3: PCM Playback Left Channel .................................................................................. 35
5.3.5. Slot 4: PCM Playback Right Channel ................................................................................ 35
5.3.6. Slot 5: Modem Line 1 Output Channel .............................................................................. 35
5.3.7. Slot 6 - 11: DAC ................................................................................................................. 35
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STAC9752/9753
REV 3.3 1206