stac9752xxtaeb2xr Integrated Device Technology, stac9752xxtaeb2xr Datasheet - Page 20

• Manufacturer Part Number: stac9752xxtaeb2xr
• Description: Two-channel, 20-bit, Ac ?97 2.3 Codecs With Microphone And Jack Sensing
• Manufacturer: Integrated Device Technology

3. TYPICAL CONNECTION DIAGRAM
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
*OPTIONAL
1 µF*
820 pF
820 pF
Note:
Note: The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at about
0.1 µF
0.1 µF
to10 K external pullup. Do NOT leave Pin 48 floating.
2.5 V. The name of the pin in the AC’97 specification is CD_GND, and this has confused many
designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to ground
will change the internal bias of the entire CODEC, and cause serious distortion. If there is no analog CD
input, then this pin can be No-Connect.
Pin 48: To Enable SPDIF, use an 1 K to10 K external pulldown. To Disable SPDIF, use an 1 K
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
3 2
2 9
3 0
PC_BEEP
PHONE
AUX_L
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_GND
CD_R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
CAP2
AFILT1
AFILT2
1 µF
25
AVdd1
26
AVss1
Figure 9. Typical Connection Diagram
AVdd2
AVss2
3 8
0.1 µF
4 2
*OPTIONAL
STAC9753
DVss1
4
2
*
20
0.1 µF
Ferrite Bead
DVss2
7
1
DVdd1
DVdd2
9
LINE_OUT_R
SDATA_OUT
LINE_OUT_L
1 µF
M O N O _ O U T
H P _ O U T _ R
HP_OUT_L
H P _ C O M M
SDATA_IN
VREFOUT
XTL_OUT
BIT_CLK
RESET#
XTL_IN
GPIO1
GPIO0
SPDIF
SYNC
EAPD
V R E F
STAC9752/9753
CID0
CID1
plane as close to codec
N C
N C
N C
0.1 µF
Ground
*Terminate ground
Analog
as possible
2
3
5
6
8
10
11
45
46
47
28
27
31
33
34
48
44
43
35
36
37
39
4 0
41
3.3V ± 5%
0
G r o u n d
Digital
OPTIONAL
HP_COMM should be tied to
ground at the headphone pin.
TUNE TO LAYOUT
22
24.576 MHz
(Near Clk source)
1 µF
27 pF
27 pF
2 7 p F
Filter
EMI
CLOCK_IN*
*Add resistive divider
when using 5V clock.
REV 3.3 1206