stac9752xxtaeb2xr Integrated Device Technology, stac9752xxtaeb2xr Datasheet - Page 19
stac9752xxtaeb2xr
Manufacturer Part Number
stac9752xxtaeb2xr
Description
Two-channel, 20-bit, Ac ?97 2.3 Codecs With Microphone And Jack Sensing
Manufacturer
Integrated Device Technology
Datasheet
1.STAC9752XXTAEB2XR.pdf
(95 pages)
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Note:
IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
2.2.7.
2.2.8.
1.
2.
3.
All AC-Link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the trailing edge
of RESET# causes the STAC9752/9753 AC-Link outputs to go high-impedance which is suitable for ATE in circuit testing.
Once the test mode has been entered, the STAC9752/9753 must be issued another RESET# with all AC-Link signals low
to return to the normal operating mode.
The pound sign (#) appended to the end of a signal name denotes that the signal is active low.
End of Slot 2 to BIT_CLK, SDATA_IN low
Setup to trailing edge of RESET# (also applies to SYNC)
Rising edge of RESET# to Hi-Z delay
AC-Link Low Power Mode Timing
ATE Test Mode
Figure 7. AC-Link Low Power Mode Timing
Parameter
Parameter
SDATA_IN, BIT_CLK
Figure 8. ATE Test Mode Timing
SDATA_OUT
SDATA_OUT
SDATA_IN
BIT_CLK
RESET#
SYNC
19
Note: BIT_CLK not to scale
Write to
Slot 1
0x20
Toff
Data PR4
Slot 2
Ts2_pdown
Tsetup2rst
Symbol
Symbol
Toff
Tsetup2rst
Don't care
Ts2_pdown
STAC9752/9753
15.0
Min
Min
Hi-Z
-
-
Typ
Typ
-
-
-
Max
Max
25.0
1.0
-
REV 3.3 1206
Units
Units
ns
ns
s
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