zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 88
![no-image](/images/manufacturer_photos/0/7/727/zarlink_semiconductor_sml.jpg)
zl50018gag2
Manufacturer Part Number
zl50018gag2
Description
2 K Digital Switch With Enhanced Stratum 3 Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50018GAG2.pdf
(136 pages)
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Quantity
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Part Number:
ZL50018GAG2
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TECCOR
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FML
External Read Only Address: 0069
15
R3
Bit
15
14
13
12
11
10
9
8
7
6
5
FMU
14
R3
R3FMU
R2FMU
R1FMU
R3FML
R2FML
R1FML
Name
R3FU
R2FU
R3FL
R2FL
R1FL
13
R3
FL
Table 57 - Reference Failure Status Register (RSR) Bits - Read Only
12
R3
FU
Reference 3 Multi-period Lower Limit Fail Bit: If the device sets this bit to high, the
input REF3 fails the multi-period lower limit check. (See Table 13, “Default Multi-period
Hysteresis Limits” on page 47)
Reference 3 Multi-period Upper Limit Fail Bit: If the device sets this bit to high, the
input REF3 fails the multi-period upper limit check. (See Table 13, “Default
Multi-period Hysteresis Limits” on page 47)
Reference 3 Single Period Lower Limit Fail Bit: If the device sets this bit to high, the
input REF3 fails the single-period lower limit check. (See Table 13, “Default
Multi-period Hysteresis Limits” on page 47)
Reference 3 Single Period Upper Limit Fail Bit: If the device sets this bit to high, the
input REF3 fails the single-period upper limit check. (See Table 13, “Default
Multi-period Hysteresis Limits” on page 47)
Reference 2 Multi-period Lower Limit Fail Bit: If the device sets this bit to high, the
input REF2 fails the multi-period lower limit check. (See Table 13, “Default Multi-period
Hysteresis Limits” on page 47)
Reference 2 Multi-period Upper Limit Fail Bit: If the device sets this bit to high, the
input REF2 fails the multi-period upper limit check. (See Table 13, “Default
Multi-period Hysteresis Limits” on page 47)
Reference 2 Single Period Lower Limit Fail Bit: If the device sets this bit to high, the
input REF2 fails the single-period lower limit check. (See Table 11, “Values for Single
Period Limits” on page 45)
Reference 2 Single Period Upper Limit Fail Bit: If the device sets this bit to high, the
input REF2 fails the single-period upper limit check. (See Table 11, “Values for Single
Period Limits” on page 45)
Reference 1 Multi-period Lower Limit Fail Bit: If the device sets this bit to high, the
input REF1 fails the multi-period lower limit check. (See Table 13, “Default Multi-period
Hysteresis Limits” on page 47)
Reference 1 Multi-period Upper Limit Fail Bit: If the device sets this bit to high, the
input REF1 fails the multi-period upper limit check. (See Table 13, “Default
Multi-period Hysteresis Limits” on page 47)
Reference 1 Single Period Lower Limit Fail Bit: If the device sets this bit to high, the
input REF1 fails the single-period lower limit check. (See Table 11, “Values for Single
Period Limits” on page 45)
H
FML
11
R2
FMU
10
R2
R2
FL
9
Zarlink Semiconductor Inc.
ZL50018
R2
FU
8
88
FML
R1
7
Description
FMU
R1
6
R1
FL
5
R1
FU
4
FML
R0
3
FMU
R0
2
Data Sheet
R0
FL
1
R0
FU
0
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