zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 71

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

Note: Note 1: Output frequency offset, relative to master clock, will be represented as the following:
Note: The default value is ±20 ppm (’h0370/CFN = 20 ppm).
15 - 14
Reset Value: 0370
External Read Only Address: 0045
External Read/Write Address: 0046
14 - 0
13 - 0
Bit
Bit
15
15
15
0
0
+10 ppm: CFN x 0.00001 = 440 = 01B8
-10 ppm: CFN x (-0.00001) = -440 = 7E48
FOF
14
14
14
FOF14 - 0
0
FLR13 - 0
Unused
Unused
Name
Name
H
FOF
FLR
13
(see Note)
13
13
13
Table 34 - Frequency Offset Register (FOR) Bits - Read Only
FOF
Reserved. In normal functional mode, this bit is zero.
Frequency Offset Bits: The binary value of these bits represents the current deviation
of the DPLL output from its center frequency. Defined in same units as CFN in the 2's
complement format.
In the software fast mode these bits do not represent frequency offset since the internal
filter and phase alignment speed (phase slope) limiter are not used.
FLR
Reserved. In normal functional mode, these bits MUST be set to zero.
Frequency Lock Range Bits: If not in the limiter bypass mode, the binary value of these
bits defines the maximum allowed deviation of the DPLL output from its center frequency.
If the DPLL limiter bypass is set in the Bandwidth Control Register, the DPLL output fre-
quency can exceed the value specified by these bits, since the proportional value of ref-
erence-to-feedback difference is predominant to the integration value in that case.
Defined in same units as CFN (unsigned).
12
12
12
12
Table 35 - Frequency Locking Range Register (FLRR) Bits
H
H
FOF
FLR
11
11
11
11
FOF
FLR
10
10
10
10
H
H
FOF
FLR
9
9
9
9
Zarlink Semiconductor Inc.
ZL50018
FOF
FLR
8
8
8
8
71
FOF
FLR
7
7
7
7
Description
Description
FOF
FLR
6
6
6
6
FOF
FLR
5
5
5
5
FOF
FLR
4
4
4
4
FOF
FLR
3
3
3
3
FOF
FLR
2
2
2
2
Data Sheet
FOF
FLR
1
1
1
1
FOF
FLR
0
0
0
0