zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 58

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

15 - 2
External Read/Write Address: 0001
External Read/Write Address: 0002
Reset Value: 0000
Reset Value: 0000
Bit
Bit
0
1
0
15
0
15
0
14
SRSTDPLL
0
SRSTSW
Unused
14
MBPS
Name
Name
0
H
H
13
0
Table 19 - Internal Mode Selection Register (IMS) Bits (continued)
13
0
12
0
Memory Block Programming Start
A zero to one transition of this bit starts the memory block programming function. The
MBPS and BPD2 - 0 bits in this register must be defined in the same write operation.
Once the MBPE bit in the Control Register is set to high, the device requires two
frames to complete the block programming. After the programming function has fin-
ished, the MBPS bit returns to low, indicating the operation is completed. When MBPS
is high, MBPS or MBPE can be set to low to abort the programming operation.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started. As long as this bit is high, the user must maintain the same logical
value to the other bits in this register to avoid any change in the device setting.
Reserved. In normal functional mode, these bits MUST be set to zero.
Software Reset Bit for Switch
When this bit is low, data switching blocks are in normal operation. When this bit is
high, data switching blocks are in software reset state.
Refer to Table 17, “Address Map for Registers (A13 = 0)” on page 52 for details
regarding which registers are affected.
Software Reset Bit for DPLL
DPLL block is in software reset state.
Refer to Table 17, “Address Map for Registers (A13 = 0)” on page 52 for details
regarding which registers are affected.
12
When this bit is low, the DPLL block is in normal operation. When this bit is high, the
0
11
0
H
H
Table 20 - Software Reset Register (SRR) Bits
11
0
10
0
10
0
9
0
9
0
Zarlink Semiconductor Inc.
PD_EN
STIO_
8
ZL50018
8
0
58
BDH
7
7
0
Description
Description
BDL
6
0
6
5
0
RBER
EN
5
4
0
TBER
EN
4
3
0
BPD
3
2
2
0
BPD
2
1
SRST
SW
1
BPD
1
0
Data Sheet
SRST
DPLL
0
MBPS
0