zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 80
zl50018gag2
Manufacturer Part Number
zl50018gag2
Description
2 K Digital Switch With Enhanced Stratum 3 Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50018GAG2.pdf
(136 pages)
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Reset Value:F0B8
Note 1:
Note 2:
Note 1:
Note 2:
External Read/Write Address: 0052
External Read/Write Address: 0053
15 - 0
15 - 0
Reset Value: 3B9A
MNL
MNL
Bit
Bit
15
15
15
31
MNL
The default value represents near lower limit for all reference frequencies, which is -9.913 ppm (Stratum 3 compliant
value), regardless of the reference frequency.
The name ’lower’ is based on frequency.
MNL
The default value represents near lower limit for all reference frequencies, which is -9.913 ppm (Stratum 3 compliant
value), regardless of the reference frequency.
The name ’lower’ is based on frequency.
14
14
14
30
MNL15 - 0
MNL31 - 16
Name
Table 46 - Multi-period Near Lower Limit Register - Lower 16 Bits (MPNLLRL)
Table 47 - Multi-period Near Lower Limit Register - Upper 16 Bits (MPNLLRU)
Name
H
MNL
MNL
13
13
13
29
(Note 1)
H
(Note 1)
MNL
MNL
12
12
12
28
Multiple-Period Near Lower Limit Bits: Total binary value of these bits and the
MPNLLRU register bits defines the near lower limit for the multiple period count of any
reference input, minus 1. The unit of the binary value is measured in 100 MHz clock
periods.
Multiple-Period Near Lower Limit Bits: Total binary value of these bits and the
MPNLLRL register bits defines the near lower limit for the multiple period count of
any reference input, minus 1. The unit of the binary value is measured in 100 MHz
clock periods.
H
H
MNL
MNL
11
11
11
27
MNL
MNL
10
10
10
26
MNL
MNL
25
9
9
9
Zarlink Semiconductor Inc.
ZL50018
MNL
MNL
24
8
8
8
80
MNL
MNL
23
7
7
7
Description
Description
MNL
MNL
22
6
6
6
MNL
MNL
21
5
5
5
MNL
MNL
20
4
4
4
MNL
MNL
19
3
3
3
MNL
MNL
18
2
2
2
Data Sheet
MNL
MNL
17
1
1
1
MNL
MNL
16
0
0
0
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