zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 76

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

External Read/Write Address: 004B
15 - 9
Reset Value: 0000
1 - 0
External Read Only Address: 004C
Bit
Bit
15
15
0
8
7
0
14
14
0
0
FDM1 - 0
Unused
Name
Name
SLM
LST
H
13
13
Table 40 - Reference Change Control Register (RCCR) Bits (continued)
0
0
Table 41 - Reference Change Status Register (RCSR) Bits - Read Only
Force DPLL Timing Mode: These bits force the DPLL into one of the valid timing
modes.
In freerun mode, it is important that the DPLL is not also in fast lock mode (see the
BWCR register). Otherwise, the output frame pulses may not be generated correctly.
Reserved. In normal functional mode, these bits are zero.
Slew Rate Limiter Status Bit: If the device sets this bit to high, the DPLL phase
difference between the input and output clocks is changing at the slew rate limit defined
in the Slew Rate Limit Register (SRLR).
Lock Status Bit: If the device sets this bit to high, while the LDTR and LDIR registers are
programmed properly, the DPLL output clocks are locked to the selected input reference.
If this bit is low, the DPLL output clocks are not yet locked to the selected input reference.
12
12
0
0
H
H
11
11
0
0
10
10
0
0
FDM1
0
0
1
1
9
0
9
0
Zarlink Semiconductor Inc.
ZL50018
SLM
8
FDM0
8
0
0
1
0
1
76
LST
MTR
7
7
Description
Description
RFR2
PRS
DPLL TIMING MODE
6
6
1
Automatic
Holdover
Freerun
Normal
RFR1
PRS
5
5
0
RFR0
PMS
4
4
2
RES1
PMS
3
3
1
RES0
PMS
2
2
0
DPM1
Data Sheet
FDM
1
1
1
DPM0
FDM
0
0
0