zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 133

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

ZL50018
Data Sheet
Performance Characteristics Notes
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, V
at 1. 8 V and V
at 3.3 V and are for design aid only: not guaranteed and not subject to production
DD_CORE
DD_IO
testing.
1. Jitter on master clock input (XIN) is 100 ps pp or less.
2. Jitter on reference input (REF0-3) is 2 ns pp or less.
3. Normal Mode selected.
4. Holdover Mode selected.
5. Freerun Mode selected.
6. Jitter is measured without an output filter.
7. Accuracy of master clock input (XIN) is 0 ppm.
8. Accuracy of master clock input (XIN) is 100 ppm.
9. Capture range is programmed to +/-20 ppm; inaccuracy of XIN shifts this range.
µ
10. Phase alignment speed (phase slope) is programmed to 7 ns/125
s.
11. Fast lock is enabled.
12. Low pass filter is programmed to 1.9 Hz.
13. Applies to all programmable low pass filter selections of 1.9 Hz and above.
14. Any input reference switch or state switch (e.g.; REF0 to REF3, Normal to Holdover, etc.).
15. Auto-holdover is programmed to 9.913 ppm & 11.287 ppm.
16. 30 pF load on output pin.
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Zarlink Semiconductor Inc.