zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 77
zl50018gag2
Manufacturer Part Number
zl50018gag2
Description
2 K Digital Switch With Enhanced Stratum 3 Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50018GAG2.pdf
(136 pages)
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6 - 4
3 - 2
1 - 0
External Read Only Address: 004C
Bit
15
0
14
0
DPM1 - 0
RFR2 - 0
RES1 - 0
Table 41 - Reference Change Status Register (RCSR) Bits - Read Only (continued)
Name
13
0
Reference Frequency Indicator Bits: These bits represent the frequency of the
selected reference indicated by the reference bits (RES1 - 0) in this register.
Reference Select Indicator Bits: These bits indicate which one of the four reference
inputs (REF0 - 3 pins) is being selected by the device.
DPLL Timing Mode Status Bits: These bits indicate the DPLL’s timing mode status.
12
0
H
11
0
RFR2
10
0
0
0
0
0
1
1
1
1
DPM1
RES1
0
0
1
1
0
0
1
1
9
0
Zarlink Semiconductor Inc.
RFR1
0
0
1
1
0
0
1
1
ZL50018
SLM
DPM0
8
RES0
0
1
0
1
0
1
0
1
77
RFR0
0
1
0
1
0
1
0
1
LST
7
DPLL Timing Mode State
Description
Input Reference in use
RFR2
6
Selected Reference
Frequency of the
Holdover
Freerun
Normal
REF 0
REF 1
REF 2
REF 3
MTIE
16.384 MHz
RFR1
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
19.44 MHz
Reserved
5
8 kHz
RFR0
4
RES1
3
RES0
2
DPM1
Data Sheet
1
DPM0
0
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