zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 74

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Reset Value: 0002
External Read/Write Address: 004A
7 - 4
3 - 0
Bit
15
0
The default corner frequency (-3 dB point) of the low pass filter is 1.9 Hz.
To set fast lock mode, it is recommended to program the register bits as follows:
LPF3-0 ->’h8, unless a specific filter response (low pass filter characteristic) is required
FFL3-0 ->’hF
FLC3-0 ->’hF, if significant amount of jitter is not present on the active reference input
FLF_QS -> 1
BLM -> 1
In fast lock mode, it is important that the device is not also in freerun mode (see the RCCR Register). Otherwise, the
output frame pulse may not be generated correctly.
If the selected reference is 8 kHz, LPF3 - 0 should not be chosen to have corner frequency higher than 1/10 of the carrier
frequency, or 800Hz (i.e. bits LPF3 - 0 should have a value equal to or smaller than 1010).
When the FFL3 - 0 bits are used in normal locking mode (when the BLM bit is not set and the SM_FST bit in the DPLLCR
register is set), the DPLL locking time increases as the unsigned binary representation of FFL3 - 0 value increases,
maintaining given phase alignment speed (phase slope). The DPLL peaking, which is limited by some standards,
increases as well, so the FFL3 - 0 must be chosen with respect to given standard requirements.
14
0
FFL3 - 0
LPF3 - 0
Name
H
BLM
(see Note)
13
Table 39 - Bandwidth Control Register (BWCR) Bits (continued)
FLF_
Fast Frequency Lock Bits: When the BLM bit in this register is high or when SM_FST
bit in the DPLLCR register is high, value of these bits (unsigned) represents fast locking
speed of the DPLL output clocks to the active input reference. The value also represents
speed grade that internal frequency value, used in holdover mode, reaches the DPLL
output frequency. The bigger the value, the faster the locking.
When both the BLM and the SM_FST bits are low, these bits are ignored.
Low Pass Filter Control Bits: Define the DPLL low pass filter corner frequency.
QS
12
H
FLC
11
3
LPF3
FLC
10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
FLC
9
1
Zarlink Semiconductor Inc.
LPF2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ZL50018
FLC
8
0
74
LPF1
FFL
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
7
3
Description
FFL
6
2
LPF0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FFL
5
1
CORNER FREQUENCY OF
FFL
4
0
DPLL FILTER
15.54 kHz
1.94 kHz
3.88 kHz
7.77 kHz
0.47 Hz
0.95 Hz
15.2 Hz
30.4 Hz
60.7 Hz
121 Hz
243 Hz
486 Hz
971 Hz
LPF
1.9 Hz
3.8 Hz
7.6 Hz
3
3
LPF
2
2
Data Sheet
LPF
1
1
LPF
0
0