zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 78
zl50018gag2
Manufacturer Part Number
zl50018gag2
Description
2 K Digital Switch With Enhanced Stratum 3 Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50018GAG2.pdf
(136 pages)
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Note 1:
Note 2:
Note 1:
Note 2:
Reset Value: A346
15 - 0
Reset Value: 3B9A
15 - 0
External Read/Write Address: 004E
External Read/Write Address: 004F
MNU
MNU
Bit
Bit
15
15
15
31
The default value represents near upper limit for all reference frequencies, which is +9.913 ppm (Stratum 3 compliant
value), regardless of the reference frequency.
The name ’upper’ is based on frequency.
The default value represents near upper limit for all reference frequencies, which is +9.913 ppm (Stratum 3 compliant
value), regardless of the reference frequency.
The name ’upper’ is based on frequency.
MNU
MNU
14
14
14
30
MNU15 - 0
MNU31 - 16
Name
Table 43 - Multi-period Near Upper Limit Register - Upper 16 Bits (MPNULRU)
Table 42 - Multi-period Near Upper Limit Register - Lower 16 Bits (MPNULRL)
Name
H
MNU
MNU
H
13
13
13
29
(Note 1)
(Note 1)
MNU
MNU
12
12
12
28
Multiple-Period Near Upper Limit Bits: Total binary value of these bits and the
MPNULRU register bits defines the near upper limit for the multiple period count of any
reference input, minus 1. The unit of the binary value is measured in 100 MHz clock
periods.
Multiple-Period Near Upper Limit Bits: Total binary value of these bits and the
MPNULRL register bits defines the near upper limit for the multiple period count of
any reference input, minus 1. The unit of the binary value is measured in 100 MHz
clock periods.
H
H
MNU
MNU
11
11
11
27
MNU
MNU
10
10
10
26
MNU
MNU
25
9
9
9
Zarlink Semiconductor Inc.
ZL50018
MNU
MNU
24
8
8
8
78
MNU
MNU
23
7
7
7
Description
Description
MNU
MNU
22
6
6
6
MNU
MNU
21
5
5
5
MNU
MNU
20
4
4
4
MNU
MNU
19
3
3
3
MNU
MNU
18
2
2
2
Data Sheet
MNU
MNU
17
1
1
1
MNU
MNU
16
0
0
0
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