zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 109

• Manufacturer Part Number: zl50018gag2
• Description: 2 K Digital Switch With Enhanced Stratum 3 Dpll
• Manufacturer: Zarlink Semiconductor

† Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics
Note 1:
Note 2:
14
15
16
17 R/W setup to DS falling
18 Address setup to DS falling
19 Data setup to DS falling
20 CS hold after DS rising
21 R/W hold after DS rising
22 Address hold after DS rising
23 Data hold from DS rising
24 Acknowledgement delay time.
25 Acknowledgement hold time.
26 DTA drive high to HiZ
CS
DS
R/W
A0-A13
D0-D15
DTA
CS de-asserted time
DS de-asserted time
CS setup to DS falling
From DS low to DTA low:
From DS high to DTA high
Registers
Memory
High impedance is measured by pulling to the appropriate rail with R
A delay of 500
discharge C
the RESET pin is set high.
Characteristics
L
.
µ
Figure 27 - Motorola Non-Multiplexed Bus Timing - Write Access
s (see Section 17.2 on page 48) must be applied before the first microprocessor access is performed after
†
t
CSD
t
DSD
- Motorola Non-Multiplexed Bus Mode - Write Access
Sym.
t
t
t
t
t
t
t
t
t
RWS
RWH
Zarlink Semiconductor Inc.
CSD
DSD
CSH
t
CSS
t
t
t
AKD
AKH
AKZ
DH
t
AS
DS
AH
t
AS
CSS
t
RWS
t
DS
ZL50018
Min.
109
15
15
10
0
5
0
0
0
0
5
4
Typ.
VALID ADDRESS
VALID WRITE DATA
t
AKD
L
, with timing corrected to cancel time taken to
Max.
150
55
12
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
C
(Note 1)
C
C
C
(Note 1)
t
t
t
CSH
AH
RWH
L
L
L
L
L
t
AKH
Test Conditions
= 50 pF
= 50 pF, R
= 50 pF
= 50 pF
= 50 pF, R
t
DH
t
AKZ
Data Sheet
V
V
V
V
L
L
V
V
CT
CT
CT
CT
= 1 K
= 1 K
CT
CT
2