zl50018gag2 Zarlink Semiconductor, zl50018gag2 Datasheet - Page 31
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zl50018gag2
Manufacturer Part Number
zl50018gag2
Description
2 K Digital Switch With Enhanced Stratum 3 Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50018GAG2.pdf
(136 pages)
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The input delay is controlled by STIN[n]BD2-0 (bits 8 - 6) to control the bit shift and STIN[n]SMP1 - 0 (bits 5 - 4) to
control the sampling point in the Stream Input Control Register 0 - 31 (SICR0 - 31).
7.3
This feature is used to advance the output data of individual output streams with respect to the output frame
boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output
Control Register 0 - 31 (SOCR0 - 31).
By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output
frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4)
of the Stream Output Control Register 0 - 31 (SOCR0 - 31) as described in Table 63 on page 97. The output bit
advancement can vary from 0 to 7 bits.
STi[n]
FPi
STio[n]
Bit Adv = 0
(Default)
STio[n]
Bit Adv = 1
Output Advancement Programming
The first 3 bits represent STIN[n]BD2 - 0 for setting the bit delay.
The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset.
NOTE: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point).
Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point.
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
000 01
000 10
000 00 (Default)
000 11
001 01
001 10
001 00
001 11
010 01
010 10
010 00
010 11
011 01
011 10
011 00
011 11
0
4 3
Last Channel
3
Last Channel
Nominal Channel n Boundary
Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS)
2 1 0
7
Figure 15 - Input Bit Delay and Factional Sampling Point
2 1 0
7
6
7
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2
Bit Advancement = 1
Channel 0
Channel 0
5
Zarlink Semiconductor Inc.
ZL50018
4
31
3
Nominal Channel n+1 Boundary
Channel 1
Channel 1
2
1
0
Channel 2
Channel 2
Data Sheet
101 00
101 10
101 01
100 00
100 10
100 01
110 00
110 10
110 01
101 11
100 11
111 00
111 10
111 01
110 11
111 11
2 1
7
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