mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 86

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.8.2.1
The second portion of the clock recovery circuit is concerned with generating the adapx_ref signal. When the CPU
reads the information placed in the clock recovery event buffer, the clock recovery algorithm can subsequently
calculate any correction required to the rate of the adapx_ref clock. A typical configuration would see the adapx_ref
signal operating at 8 kHz. This is outputted to a PLL which multiplies the frequency up to 16.384 MHz. Finally, the
16 MHz clock is used as the driving clock for the TDM section, pll_clk (pin AB2).
The adapx_ref clocks are generated by dividing mem_clk by a 16-bit integer (712h & 71Ah) and 16-bit fraction
(714h & 71Ch). This allows a highly precise division (with mem_clk running at 50 MHz and the target clock speed
8 kHz, it gives a precision of 2.4 ppb).
The fractional divider will introduce jitter into the adapx_ref signal of a maximum of one mem_clk cycle. If it is
desired that no jitter be added by the adapx_ref module, set fraction to 0 (this will reduce precision to 160 ppm from
2.4 ppb). The integer and fraction are programmed by the clock recovery algorithm. The adapx_ref signal can be
driven onto any of the eight GPIOs on the MT90502, or to one of the ct_netrefs (see Figure 49). It can be externally
routed to a PLL used to multiply it up from 8 kHz to 16.384 MHz and then rerouted into the MT90502 on the pll_clk
pin.
2.8.3
Multiplexers
adapx_ref Clock Generation
Message Channel Circuit
ct_frame_selected
ct_c8_selected
Generator
MC Clock
Figure 48 - Message Channel
f
adapx_ref
mc_clock
Zarlink Semiconductor Inc.
MT90502
=
ct_mc_in
---------------------------------------------- -
integer
gpio_in[2]
86
f
mem_clk
0
+
fraction
-------------------- -
65536
ct_mc
Data Sheet