mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 25

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2. Write the lower address, extended_a[19:4], to register 00Ah. This write may not be required if previous value
3. Write the write data, extended_data[15:0], to register 004h. This write may not be required if previous value
4. Write write_enable, extended_parity, access_req=‘1’ and extended_a [3:1] in a single access to register 000h.
5. Read the access_req bit located in the Control Register[8] to determine when the write cycle has completed.
The software will set access_req [8] in register 000h (see Step 4 above). The hardware will reset the bit when the
data write cycle has completed. Therefore, this bit can be polled to determine when the data write cycle has
completed.
Extended Indirect Reads
1. Write the upper address, extended_a[32:20], to register 008h. This write may not be required if previous value
2. Write the lower address, extended_a[19:4], to register 00Ah. This write may not be required if previous value
3. Write write_enable = 00, access_req=‘1’ and extended_a [3:1] in a single access to register 000h.
4. Wait until access_req is cleared, then read the data from the data field extended_data[15:0], register 004h.
Optional parity check may be ascertained by performing a read on the extended_parity[15:14], register 000h.
The software will set access_req[8] register 000h and the hardware will reset it when the data is ready to be read
from register 004h.
2.1.2.2
Extended Direct Accessing employs the high and low address registers to perform page addressing. The address
within the page is provided directly by the CPU address bus. Similarly, the data is fetched/placed directly on the
CPU data bus.
Synopsis: The access address is written to registers 008h and 00Ah. This will perform only the page addressing.
Upon assertion of the address within the page, the MT90502 will read/write the data with respect to that address.
The CPU_A_DAS bit is set when the data read/write occurs. When operating the CPU interface in direct mode with
a 16-bit data bus, extended_a[19:16], are employed for the lower address word register 00Ah. However, when
operating the CPU interface in direct mode with an 8-bit data bus, bits [19:15] are used for the lower address word.
Extended Direct Writes
1. Write the upper address, extended_a[32:20], to register 008h. This write may not be required if previous value
2. Write the lower address extended_a[19:16] or [19:15] to register 00Ah. The remaining bits [15:4] or [14:4] are
3. Write write_enable[13:12] (this write may not be required if previous value holds true) and
4. Write the data value to the address within the corresponding memory page with the CPU_A_DAS bit set.
Extended Direct Reads
1. Write the upper address, extended_a[32:20], to register 008h. This write may not be required if previous value
holds true.
holds true.
holds true.
holds true.
holds true.
ignored. This write may not be required if previous value holds true.
extended_parity[15:14]. The extended parity write is optional.
holds true.
Extended Direct Accessing
Zarlink Semiconductor Inc.
MT90502
25
Data Sheet