mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 167

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 718h
Label: adapb0
Reset Value: 0001h
Adapb_keep_one_pulse_out_of_x
Adapb_clk_divisor_reset
Adapb_source
Adapb_clk_divisor_load_now
Reserved
Address: 71Ah
Label: adapb1
Reset Value: 0000h
Adapb_div_integer
Address: 71Ch
Label: adapb2
Reset Value: 0000h
adapb_div_fraction
Label
Label
Label
Table 172 - Adaptive Module B Register 2
Table 171 - Adaptive Module B Register 1
Table 170 - Adaptive Module B Register 0
Bit Position Type
Position
Position
15:0
Bit
15:0
12:11
15:14
9:0
Bit
10
13
Type
Zarlink Semiconductor Inc.
RW Adaptive module B's mem_clk divisor (integer part). Range 2
Type
PUL When written to '1', this will allow the new div_integer and
PUL Reserved. Always read as “00”
RW Adaptive module B's mem_clk divisor (fractional part).
RW This field indicates how many clock recovery points should
RW When '0', this will force the Adaptive module B's clock
RW “00” = clkrecov_pulse_b; “01” = gpio[1] (any change); “10” =
MT90502
to FFFFh.
Range 0 to FFFFh.
be received per point written to the point memory. Typically,
this value would be set to 1. Range 1 to 1024.
divisor to reset.
gpio[1] (rising edge); “11” = gpio[1] (falling edge).
div_fraction to be used.
167
Description
Description
Description
Data Sheet