mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 161
mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
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Address: 6A0h
Label: porta_address
Reset Value: 0000h
porta_add
reserved
Address: 6A2h
Label: hec_byte_control
Reset Value: 0055h
hec_mask
reserved
Address: 6A4h
Label: unknown_header_routing
Reset Value: 0000h
rxa_ncr
rxb_ncr
rxc_ncr
reserved
Label
Label
Label
Bit Position Type
Bit Position Type
Bit Position Type
15:12
15:5
15:8
11:8
4:0
7:0
3:0
7:4
Table 158 - Unknown Header Routing Register
Table 157 - HEC Byte Control Register
Table 156 - Port A Address Register
RW The address to which the chip will respond in UTOPIA level 2
RW Reserved. Must always be “0000_0000_000”
RW The value by which the HEC byte will be XORed before being
RW Reserved. Must always be “0000_0000”
RW Routing of non-OAM cells from port A that fail the VPI-VCI match
RW Routing of non-OAM cells from port B that fail the VPI-VCI match
RW Routing of non-OAM cells from port C that fail the VPI-VCI match
RW Reserved. Must always be “0000”
addressing.
transmitted.
and mask test. “xxx1” = send to port A, “xx1x” = send to port B,
“x1xx” = send to port C, “1xxx” = send to AAL0.
and mask test. “xxx1” = send to port A, “xx1x” = send to port B,
“x1xx” = send to port C, “1xxx” = send to AAL0.
and mask test. “xxx1” = send to port A, “xx1x” = send to port B,
“x1xx” = send to port C, “1xxx” = send to AAL0.
Zarlink Semiconductor Inc.
MT90502
161
Description
Description
Description
Data Sheet
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