mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 177

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 776h
Label: mastership_hidden1
Reset Value: 0000h
h100_check_automatic_override
h100_min_mem_clk_ct_c8_override
h100_max_mem_clk_ct_c8_override
h100_sample_tristate_override
Reserved
Address: 778h
Label: mastership_hidden2
Reset Value: 0000h
h100_samp_clk_delay_flops
h100_samp_clk_delay_buff
h100_oe_clk_delay_flops
h100_oe_clk_delay_buff
Label
Label
Table 186 - H.100/H.110 Master Hidden Register 1
Table 187 - H.100/H.110 Master Hidden Register 2
Position
15:12
11:8
7:4
Bit
3:0
Position
15:12
10:6
5:1
Bit
11
0
Type
Zarlink Semiconductor Inc.
RW Number of flops used = 8 + value of this register. “1111” is
RW “1111” is reserved for selecting rising edge ct_c8 clock
RW Number of flops used = 8 + value of this register
RW
MT90502
Type
WO When '1', the following two field will control the ct_c8
WO When '1', the values in the following registers will be
WO Reserved. Always read as “0000”
RW minimum period (in mem_clk cycles) between 2 H100
RW Maximum period (in mem_clk cycles) between 2 H100
reserved for selecting falling edge ct_c8 clock
177
frequency checker.
ct_c8 clock rising edges.
ct_c8 clock rising edges.
used to control the sampling and tri-state delays.
Description
Description
Data Sheet