mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 2

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

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Applications
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Description
The MT90502 Multi-Channel AAL2 SAR bridges a standard TDM (Time Division Multiplexed) backplane to a
standard ATM (Asynchronous Transfer Mode) bus. The device provides the CPS (Common Part Sublayer) and
SAR (Segmentation and Reassembly) engines. The MT90502 has the capability of simultaneously processing
1023 bi-directional CIDs (AAL2 Channel Identifiers) and 1023 bi-directional VCs (Virtual Circuits). The device can
be connected directly to an H.110 compatible bus. The TDM bus consists of 32 bi-directional serial data streams
operating at 2.048, 4.096, or 8.192 Mbits/s.
The MT90502 directly accepts G.711 PCM (Pulse Code Modulation) and G.726 ADPCM (Adaptive Differential Pulse
Code Modulation) traffic for packetisation. For these two data formats, the device also implements silence
suppression and comfort noise generation. To support other voice compression algorithms, the MT90502 connects
directly to commercially available DSPs through synchronous serial data streams. The Variable Bit Rate (VBR)
traffic is HDLC encapsulated and carried over the serial data streams.
The interface to the ATM domain is provided by three UTOPIA Level 1 ports (Ports A, B, and C). All three of the
UTOPIA ports can operate in ATM (master) or PHY (slave) mode. Ports A and B combined, architects a compliant
UTOPIA Level 2 Multi-PHY port. The MT90502 provides the capability of routing ATM cells to different UTOPIA
interfaces, SAR engine or CPU. This feature can be used to connect another MT90502 (to support up to 2046 CID
channels or 2046 phone calls) and/or to connect an external AAL1 and/or AAL5 SAR.
Gateway
ATM Edge Switch
Next Generation Digital Loop Carrier
Multiservice Switching Platform
3rd Generation Mobile System Equipment
Comfort noise generation
Capability to inject and recover CPS packets through the CPU host processor bus
8-bit or 16-bit microprocessor port, configurable to Motorola or Intel timing
Single rail 3.3 V, 456 PBGA
IEEE 1149 (JTAG) interface
Zarlink Semiconductor Inc.
MT90502
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Data Sheet