mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 15

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

D12
D14
A13
B13
C15, B15, A15, C14, B14, A14,
D13, C13
D15
A9
C12
B9
C9
A12, C11, B11, A11, D10, C10,
B10, A10
B12
D17
C17
B17
D5
D8
A6
B6
B8, A8, D7, C7, B7, A7, D6, C6
C8
E4
A4
Pins
rst
Table 2 - UTOPIA Interface Pins (continued)
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
txa_clk
txa_soc
1. txa_enb
2. txa_clav
1. txa_clav
2. txa_enb
txa_d[7:0]
txa_prty
rxa_clk
rxa_soc
1. rxa_enb
2. rxa_clav
1. rxa_clav
2. rxa_enb
rxa_d[7:0]
rxa_prty
txb_led
rxb_led
rxb_alarm
txb_clk
txb_soc
1. txb_enb
2. txb_clav
1. txb_clav
2. txb_enb
txb_d[7:0]
txb_prty
rxb_clk
1. rxb_soc
2. txa_addr[4]
Name
Zarlink Semiconductor Inc.
MT90502
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL (F)
LVTTL 6 mA (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL 12 mA (F)
LVTTL 12 mA (F)
LVTTL (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL (F)
Type
UTOPIA port A TX clock
UTOPIA port A TX Start of Cell
1. UTOPIA port A TX Enable in
ATM mode
2. UTOPIA port A TX Cell
Available in PHY mode
1. UTOPIA port A TX Cell
Available in ATM mode
2. UTOPIA port A TX Enable in
PHY mode
UTOPIA port A TX Data bus
UTOPIA port A TX Parity
UTOPIA port A RX clock
UTOPIA port A RX Start of Cell
1. UTOPIA port A RX Enable in
ATM mode
2. UTOPIA port A RX Cell
Available in PHY mode
1. UTOPIA port A RX Cell
Available in ATM mode
2. UTOPIA port A RX Enable in
PHY mode
UTOPIA port A RX Data bus
UTOPIA port B TX LED
UTOPIA port B RX LED
UTOPIA port B PHY alarm
UTOPIA port B TX clock
UTOPIA port B TX Start of Cell
1. UTOPIA port B TX Enable in
ATM mode
2. UTOPIA port B TX Cell
Available in PHY mode
1. UTOPIA port B TX Cell
Available in ATM mode
2. UTOPIA port B TX Enable in
PHY mode
UTOPIA port B TX Data bus
UTOPIA port B TX Parity
UTOPIA port B RX clock
1. UTOPIA port B RX Start of Cell
2. txa_addr[4] when port A and B
are combined
UTOPIA port A RX Parity
Description
Data Sheet