mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 114

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

3.0
3.1
Address: 100h
Label: control
Reset Value: 0000
sreset
low_latency_cpu_accesses
reserved
test_status
Address: 102h
Label: status0
Reset Value: 0000h
reserved
internal_read_timeout
cpu_read_done
reserved
CPU Register
Register List
Label
Label
Bit Position
Bit Position
15:5
2:0
3
4
14:2
15
0
1
Table 35 - CPU Control Register
Table 36 - CPU Status Register
Type
ROL Reserved. Always read as “000”
ROL Internal device time-out. Generally occurs when a clock is
ROL This bit is set when a burst of reads is completed. This bit may
ROL Reserved. Always read as “0000_0000_000”
Zarlink Semiconductor Inc.
Type
RW
RW
RW
TS
MT90502
missing or misbehaving.
be used to generate an interrupt after a large read burst has
completed (in indirection). For small read bursts, it is not very
useful since there is not enough time for the CPU to do anything
between the time it starts the read and the time that the read
ends.
Active low software reset. Resets the whole chip except the
CPU interface. Once low, all registers will be cleared except
for CPU registers and Main Registers.
When '1', no caching will be done in the CPU Interface, thus
guaranteeing a higher average access time, but a lower
worst case access time.
Reserved. Must always be “0000_0000_0000_0”
Reserved. Must always be “0”.
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Description
Description
Data Sheet