mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 132
mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
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Address: 256h
Label: sdram_conf3
Reset Value: 0000h
sdram_add_idle
reserved
Address: 258h
Label: sdram_conf4
Reset Value: 0000h
sdram_add_man
reserved
Address: 25Ah
Label: sdram_conf5
Reset Value: 003Fh
sdram_cas_idle
sdram_ras_idle
sdram_we_idle
sdram_cas_man
sdram_ras_man
Label
Label
Label
Bit Position
Bit Position
Bit Position
15:14
13:0
15:14
13:0
0
1
2
3
4
Table 66 - SDRAM Configuration Register 3
Table 67 - SDRAM Configuration Register 4
Table 68 - SDRAM Configuration Register 5
Type
RW While sdram_enable is '0', the value placed in this register will be
RW Reserved. Must always be “00”
Type
Type
RW
RW
RW
RW
RW
RW
RW
Zarlink Semiconductor Inc.
put on the address lines.
MT90502
While sdram_enable is '0', the value placed in this register will
be put on the address lines for 1 cycle if
sdram_manual_access is written to '1'.
Reserved. Must always be “00”
While sdram_enable is '0', the value placed in this register will
be put on the cas line.
While sdram_enable is '0', the value placed in this register will
be put on the ras line.
While sdram_enable is '0', the value placed in this register will
be put on the we line.
While sdram_enable is '0', the value placed in this register will
be put on the cas line for 1 cycle if sdram_manual_access is
written to '1'.
While sdram_enable is '0', the value placed in this register will
be put on the ras line for 1 cycle if sdram_manual_access is
written to '1'.
132
Description
Description
Description
Data Sheet
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