mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 192
mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
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t2_muxed cpu_rdy_ndtack rising edge to
t2_reads cpu_rdy_ndtack rising edge to
Symbol
t13
t15
t16
t17
t1
t4
t5
t6
t8
cpu_ale fall
cpu_ale rising edge
read_access_active rising edge
read_access_active falling edge to
cpu_rdy_ndtack falling edge
Read Access Time
read_access_active rising edge to
cpu_rdy_ndtack tri-state
read_access_active falling edge to cpu_d driven
cpu_d valid to cpu_rdy_ndtack rising edge
cpu_ale high pulse width
cpu_d valid to cpu_ale falling edge
cpu_ale falling edge to cpu_d invalid
read_access_active falling edge to
(when all CS, R/W and DS are low)
write_access_active
cpu_rdy_ndtack
Table 207 - Multiplexed CPU Interface - Intel Mode - Read Access
Figure 77 - Multiplexed CPU Interface - Motorola Mode - Write Access
cpu_d[15:0]
cpu_ale
Description
Zarlink Semiconductor Inc.
t15
t9
MT90502
t1_writes
t1_muxed
t16
t17
192
t5
t3_muxed
t3_writes2
3 * upclk - 4
upclk - 4
Min.
0
0
0
0
5
5
5
t3_writes1
Typical
t10
2 * upclk - 4 ns
t11
Table 205
Max.
see
Data Sheet
12
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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