dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 85
dspic33fj128mc204
Manufacturer Part Number
dspic33fj128mc204
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ128MC204.pdf
(412 pages)
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TABLE 6-2:
6.2
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
V
has elapsed. The delay T
device bias circuits become stable.
The device supply voltage characteristics must meet
the
requirements to
Section 31.0 “Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
© 2009 Microchip Technology Inc.
V
T
V
T
T
T
DD
POR
BOR
PWRT
FSCM
POR
BOR
Note:
crosses the V
specified
Power-on Reset (POR)
When the device exits the Reset
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
all
specification.
Symbol
starting
OSCILLATOR DELAY
operating
POR
generate
threshold and the delay T
voltage
POR
the
parameters
ensures the internal
POR.
POR threshold
POR extension time
BOR threshold
BOR extension time
Programmable power-up time delay
Fail-Safe Clock Monitor Delay
and
rise
Refer
within
POR
rate
Parameter
Preliminary
to
6.2.1
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the V
(V
circuit keeps the device in Reset until V
V
delay T
becomes stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
V
operation. The PWRT provides power-up time delay
(T
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
The power-up timer delay (T
the
(FPWRT<2:0>)
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 28.0 “Special
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
reset delay (T
rises above the V
BOR
DD
PWRT
DD
should rise to acceptable levels for full-speed
< V
threshold and the delay T
Power-on
) to ensure that the system power supplies have
BOR
BOR
Brown-out Reset (BOR) and
Power-up timer (PWRT)
1.8V nominal
30 μs maximum
2.5V nominal
100 μs maximum
0-128 ms nominal
900 μs maximum
) for proper device operation. The BOR
BOR
ensures the voltage regulator output
BOR
bits
+ T
Reset
PWRT
trip point
in
) is initiated each time V
the
PWRT
Timer
Value
BOR
POR
) is programmed by
DS70291C-page 83
has elapsed. The
Value
Configuration
DD
DD
is too low
crosses
Select
DD
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