dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 52
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dspic33fj128mc204
Manufacturer Part Number
dspic33fj128mc204
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ128MC204.pdf
(412 pages)
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TABLE 4-15:
TABLE 4-16:
TABLE 4-17:
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
Legend:
ADC1BUF0
AD1CON1
AD1CON2
AD1CON3
AD1CHS123
AD1CHS0
AD1PCFGL
AD1CSSL
AD1CON4
Legend:
SFR Name
SFR Name
File Name
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
Addr
032C
SFR
0240
0242
0244
0248
SFR
0260
0262
0264
0268
Addr
0300
0320
0322
0324
0326
0328
0330
0332
SPI1 REGISTER MAP
SPI2 REGISTER MAP
ADC1 REGISTER MAP FOR dsPIC33FJ64MC202/802, dsPIC33FJ128MC202/802 AND dsPIC33FJ32MC302
FRMEN
FRMEN
CH0NB
ADON
ADRC
Bit 15
SPIEN
Bit 15
SPIEN
Bit 15
—
—
—
—
—
—
VCFG<2:0>
Bit 14
SPIFSD
SPIFSD
—
—
—
—
—
—
—
Bit 14
Bit 14
—
—
—
—
ADSIDL ADDMABM
Bit 13
—
—
—
—
—
—
FRMPOL
FRMPOL
SPISIDL
SPISIDL
Bit 13
Bit 13
—
—
Bit 12
—
—
—
—
—
DISSCK
DISSCK
Bit 12
Bit 12
—
—
—
—
Bit 11
DISSDO
DISSDO
—
—
—
—
—
—
Bit 11
Bit 11
—
—
—
—
CH0SB<4:0>
SAMC<4:0>
CSCNA
AD12B
Bit 10
CH123NB<1:0>
MODE16
MODE16
—
—
—
Bit 10
Bit 10
—
—
—
—
Bit 9
SPI1 Transmit and Receive Buffer Register
SPI2 Transmit and Receive Buffer Register
—
—
—
FORM<1:0>
CHPS<1:0>
Bit 9
SMP
Bit 9
SMP
—
—
—
—
CH123SB
Bit 8
ADC Data Buffer 0
—
—
—
Bit 8
Bit 8
CKE
CKE
—
—
—
—
CH0NA
BUFS
Bit 7
—
—
—
—
SSEN
SSEN
Bit 7
Bit 7
—
—
—
—
SSRC<2:0>
SPIROV
SPIROV
Bit 6
—
—
—
—
—
—
Bit 6
Bit 6
CKP
CKP
—
—
PCFG5
CSS5
MSTEN
MSTEN
Bit 5
Bit 5
Bit 5
—
—
—
—
—
—
—
PCFG4
CSS4
Bit 4
Bit 4
Bit 4
—
—
—
—
—
—
—
ADCS<7:0>
SMPI<3:0>
SPRE<2:0>
SPRE<2:0>
SIMSAM
PCFG3
CSS3
Bit 3
Bit 3
Bit 3
—
—
—
—
—
—
CH0SA<4:0>
PCFG2
ASAM
CSS2
Bit 2
Bit 2
Bit 2
CH123NA<1:0>
—
—
—
—
DMABL<2:0>
FRMDLY
FRMDLY
PCFG1
SPITBF
SPITBF
SAMP
BUFM
CSS1
Bit 1
Bit 1
Bit 1
PPRE<1:0>
PPRE<1:0>
CH123SA
SPIRBF
SPIRBF
PCFG0
DONE
ALTS
CSS0
Bit 0
Bit 0
Bit 0
—
—
Resets
Resets
Resets
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
All
All
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