dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 25

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

3.0
3.1
The
dsPIC33FJ64MCX02/X04,
dsPIC33FJ128MCX02/X04 CPU module has a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set, including significant support for DSP.
The CPU has a 24-bit instruction word with a variable
length opcode field. The Program Counter (PC) is
23 bits wide and addresses up to 4M x 24 bits of user
program memory space. The actual amount of program
memory implemented varies by device. A single-cycle
instruction prefetch mechanism is used to help main-
tain throughput and provides predictable execution. All
instructions execute in a single cycle, with the excep-
tion of instructions that change the program flow, the
double-word move (MOV.D) instruction and the table
instructions. Overhead-free program loop constructs
are supported using the DO and REPEAT instructions,
both of which are interruptible at any time.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04, and
dsPIC33FJ128MCX02/X04 devices have sixteen, 16-bit
working registers in the programmer’s model. Each of
the working registers can serve as a data, address or
address offset register. The 16th working register
(W15) operates as a software Stack Pointer (SP) for
interrupts and calls.
There
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the
dsPIC33FJ64MCX02/X04,
dsPIC33FJ128MCX02/X04 is capable of executing a
data (or program data) memory read, a working
register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
© 2009 Microchip Technology Inc.
Note:
are
CPU
Overview
This data sheet summarizes the features
of
dsPIC33FJ64MCX02/X04,
dsPIC33FJ128MCX02/X04 families of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F Family Reference Manual”,
Section 2. “CPU” (DS70204), which is
available from the Microchip website
(www.microchip.com).
two
classes
dsPIC33FJ32MC302/304,
dsPIC33FJ32MC302/304,
of
dsPIC33FJ32MC302/304,
instruction
in
and
and
and
Preliminary
the
A block diagram of the CPU is shown in Figure 3-1, and
the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 is shown in Figure 3-2.
3.2
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.3
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP
instructions
instructions and have been designed for optimal
real-time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
Data Addressing Overview
DSP Engine Overview
programmer’s
operate
seamlessly
model
DS70291C-page 23
with
for
all
other
the