dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 84

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

FIGURE 6-2:
DS70291C-page 82
Oscillator Clock
Device Status
POR Reset
BOR Reset
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
SYSRST
FSCM
V
DD
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
active until V
the V
becomes stable.
period of time (T
at the appropriate level for full-speed operation. After the delay T
inactive, which in turn enables the selected oscillator to start generating clock cycles.
Table 6-1. Refer to Section 9.0 “Oscillator Configuration” for more information.
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
is ready and the delay T
1
SYSTEM RESET TIMING
BOR
2
threshold and the delay T
DD
T
crosses the V
PWRT
V
POR
POR
) after a BOR. The delay T
FSCM
POR
elapsed.
threshold and the delay T
Preliminary
Vbor
BOR
V
BOR
has elapsed. The delay T
T
PWRT
T
BOR
3
Reset
Time
PWRT
ensures that the system power supplies have stabilized
T
OSCD
POR
has elapsed.
PWRT
BOR
T
OST
4
ensures the voltage regulator output
has elapsed, the SYSRST becomes
© 2009 Microchip Technology Inc.
T
LOCK
5
6
Run
DD
T
FSCM
crosses