dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 248

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 21-1:
DS70291C-page 246
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10-8
bit 7-5
bit 4
bit 3
bit 2-1
bit 0
U-0
R-1
—
OPMODE<2:0>
Unimplemented: Read as ‘0’
CSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
ABAT: Abort All Pending Transmissions bit
1 = Signal all transmit buffers to abort transmission.
0 = Module will clear this bit when all transmissions are aborted
Reserved: Do not use
1 = CAN F
0 = CAN F
REQOP<2:0>: Request Operation Mode bits
000 = Set Normal Operation mode
001 = Set Disable mode
010 = Set Loopback mode
011 = Set Listen Only Mode
100 = Set Configuration mode
101 = Reserved
110 = Reserved
111 = Set Listen All Messages mode
OPMODE<2:0>: Operation Mode bits
000 = Module is in Normal Operation mode
001 = Module is in Disable mode
010 = Module is in Loopback mode
011 = Module is in Listen Only mode
100 = Module is in Configuration mode
101 = Reserved
110 = Reserved
111 = Module is in Listen All Messages mode
Unimplemented: Read as ‘0’
CANCAP: CAN Message Receive Timer Capture Event Enable bit
1 = Enable input capture based on CAN message receive
0 = Disable CAN capture
Unimplemented: Read as ‘0’
WIN: SFR Map Window Select bit
1 = Use filter window
0 = Use buffer window
U-0
R-0
—
CiCTRL1: ECAN™ CONTROL REGISTER 1
CAN
CAN
C = Writable bit, but only ‘0’ can be written to clear the bit r = Bit is Reserved
W = Writable bit
‘1’ = Bit is set
clock is F
clock is F
CSIDL
R/W-0
R-0
CY
OSC
R/W-0
ABAT
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CANCAP
R/W-0
r-0
—
R/W-1
U-0
—
© 2009 Microchip Technology Inc.
REQOP<2:0>
x = Bit is unknown
R/W-0
U-0
—
R/W-0
R/W-0
WIN
bit 8
bit 0