dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 286
dspic33fj128mc204
Manufacturer Part Number
dspic33fj128mc204
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ128MC204.pdf
(412 pages)
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23.4
The DAC clock signal clocks the internal logic of the
Audio DAC module. The data sample rate of the Audio
DAC is an integer division of the rate of the DAC clock.
The DAC clock is generated via a clock divider circuit
that accepts an auxiliary clock from the auxiliary oscil-
lator. The divisor ratio is programmed by clock divider
FIGURE 23-1:
FIGURE 23-2:
DS70291C-page 284
Count (DAC1RDAT)
Output (DAC1RN)
Output (DAC1RP)
DAC CLOCK
Negative DAC
Positive DAC
DAC input
CONTROL
Note 1:
0.65
0x0000
0.65
0xFFFF
2.65
2.65
1.65
BLOCK DIAGRAM OF AUDIO DIGITAL-TO-ANALOG (DAC) CONVERTER
AUDIO DAC OUTPUT FOR RAMP INPUT (UNSIGNED)
V
V
DD
If DAC1RDAT and DAC1LDAT are empty, data will be taken from the DACDFLT register.
DD
/2
/2
DACFDIV<6:0>
ACLK
1.65
DAC1RDAT
DAC1LDAT
CLK DIV
Preliminary
DACDFLT
bits (DACFDIV<6:0>) in the DAC Control register
(DAC1CON). The resulting DAC clock must not exceed
25.6 MHz. If lower sample rates are to be used, then
the DAC filter clock frequency may be reduced to
reduce power consumption. The DAC clock frequency
is 256 times the sampling frequency.
Note 1
Note 1
D/A
D/A
© 2009 Microchip Technology Inc.
Amp
Amp
Right Channel
Left Channel
DAC1RM
DAC1RP
DAC1RN
DAC1LM
DAC1LP
DAC1LN
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