dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 201

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

14.0
The Input Capture module is useful in applications that
requires frequency (period) and pulse measurement.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 devices support
up to four input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1.
FIGURE 14-1:
© 2009 Microchip Technology Inc.
Note:
- Capture timer value on every falling edge of
- Capture timer value on every rising edge of
Simple Capture Event modes:
input at ICx pin
input at ICx pin
ICx pin
INPUT CAPTURE
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
This data sheet summarizes the features
of
dsPIC33FJ64MCX02/X04,
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a
comprehensive
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, Section 12. “Input
Capture” (DS70198), which is available
from
(www.microchip.com).
the
the
INPUT CAPTURE BLOCK DIAGRAM
dsPIC33FJ32MC302/304,
Falling Edge Mode
(16th Rising Edge)
Rising Edge Mode
(4th Rising Edge)
reference
Prescaler Mode
Prescaler Mode
Edge Detection
Microchip
Wake-up Mode
Sleep/Idle
Mode
families
source.
website
and
101
100
011
010
Preliminary
001
ICM<2:0>
To
of
CaptureEvent
2.
3.
Each input capture channel can select one of two 16-
bit timers (Timer2 or Timer3) for the time base. The
selected timer can use either an internal or external
clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Use of input capture to provide additional sources
ICTMR
- Capture timer value on every 4th rising edge
- Capture timer value on every 16th rising
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
of external interrupts
Note:
Capture timer value on every edge (rising and
falling)
Prescaler Capture Event modes:
of input at ICx pin
edge of input at ICx pin
4 buffer locations are filled
FIFO CONTROL
TMR2 TMR3
ICxBUF
ICI<1:0>
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to ‘1’ (ICI<1:0> = 00)
/N
FIFO
ICM<2:0>
001
111
To CPU
(In IFSx Register)
Set Flag ICxIF
DS70291C-page 199