dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 404

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

ECAN Registers
ECAN Transmit/Receive Error Count Register (CiEC) ..... 251
ECAN TX/RX Buffer m Control Register (CiTRmnCON) .. 262
Electrical Characteristics................................................... 337
Enhanced CAN Module..................................................... 241
Equations
Errata .................................................................................. 11
F
Flash Program Memory....................................................... 71
Flexible Configuration ....................................................... 315
DS70291C-page 402
CiINTE register ......................................................... 250
CiINTF register.......................................................... 249
CiRXFnEID register .................................................. 257
CiRXFnSID register .................................................. 256
CiRXFUL1 register .................................................... 260
CiRXFUL2 register .................................................... 260
CiRXMnEID register.................................................. 259
CiRXMnSID register.................................................. 259
CiRXOVF1 register ................................................... 261
CiRXOVF2 register ................................................... 261
CiTRmnCON register ................................................ 262
CiVEC register .......................................................... 246
ECAN1 Register Map (C1CTRL1.WIN = 0 or 1) ......... 53
ECAN1 Register Map (C1CTRL1.WIN = 0) ................ 53
ECAN1 Register Map (C1CTRL1.WIN = 1) ................ 54
Frame Types ............................................................. 241
Modes of Operation .................................................. 243
Overview ................................................................... 241
Acceptance Filter Enable Register (CiFEN1)............ 253
Acceptance Filter Extended Identifier
Acceptance Filter Mask Extended Identifier
Acceptance Filter Mask Standard Identifier
Acceptance Filter Standard Identifier
Baud Rate Configuration Register 1 (CiCFG1) ......... 251
Baud Rate Configuration Register 2 (CiCFG2) ......... 252
Control Register 1 (CiCTRL1) ................................... 244
Control Register 2 (CiCTRL2) ................................... 245
FIFO Control Register (CiFCTRL) ............................ 247
FIFO Status Register (CiFIFO) ................................. 248
Filter 0-3 Buffer Pointer Register (CiBUFPNT1) ....... 253
Filter 12-15 Buffer Pointer Register (CiBUFPNT4) ... 255
Filter 15-8 Mask Selection Register (CiFMSKSEL2). 258
Filter 4-7 Buffer Pointer Register (CiBUFPNT2) ....... 254
Filter 7-0 Mask Selection Register (CiFMSKSEL1)... 257
Filter 8-11 Buffer Pointer Register (CiBUFPNT3) ..... 254
Interrupt Code Register (CiVEC) .............................. 246
Interrupt Enable Register (CiINTE) ........................... 250
Interrupt Flag Register (CiINTF) ............................... 249
Receive Buffer Full Register 1 (CiRXFUL1).............. 260
Receive Buffer Full Register 2 (CiRXFUL2).............. 260
Receive Buffer Overflow Register 2 (CiRXOVF2)..... 261
Receive Overflow Register (CiRXOVF1) .................. 261
AC ............................................................................. 346
Device Operating Frequency .................................... 140
Control Registers ........................................................ 72
Operations .................................................................. 72
Programming Algorithm .............................................. 75
RTSP Operation.......................................................... 72
Table Instructions........................................................ 71
Register n (CiRXFnEID).................................... 257
Register n (CiRXMnEID)................................... 259
Register n (CiRXMnSID)................................... 259
Register n (CiRXFnSID).................................... 256
Preliminary
I
I/O Ports............................................................................ 157
I
In-Circuit Debugger........................................................... 321
In-Circuit Emulation .......................................................... 315
In-Circuit Serial Programming (ICSP)....................... 315, 321
Input Capture .................................................................... 197
Input Change Notification ................................................. 158
Instruction Addressing Modes ............................................ 62
Instruction Set
Instruction-Based Power-Saving Modes........................... 151
Internal RC Oscillator
Internet Address ............................................................... 402
Interrupt Control and Status Registers ............................... 89
Interrupt Setup Procedures............................................... 126
Interrupt Vector Table (IVT) ................................................ 85
Interrupts Coincident with Power Save Instructions ......... 152
J
JTAG Boundary Scan Interface ........................................ 315
JTAG Interface.................................................................. 321
M
Memory Organization ......................................................... 35
Microchip Internet Web Site.............................................. 402
Modes of Operation
Modulo Addressing ............................................................. 64
Motor Control PWM .......................................................... 203
2
C
Parallel I/O (PIO) ...................................................... 157
Write/Read Timing .................................................... 158
Operating Modes ...................................................... 227
Registers .................................................................. 227
Registers .................................................................. 198
File Register Instructions ............................................ 62
Fundamental Modes Supported ................................. 63
MAC Instructions ........................................................ 63
MCU Instructions ........................................................ 62
Move and Accumulator Instructions............................ 63
Other Instructions ....................................................... 63
Overview................................................................... 328
Summary .................................................................. 325
Idle ............................................................................ 152
Sleep ........................................................................ 151
Use with WDT........................................................... 320
IECx ............................................................................ 89
IFSx ............................................................................ 89
INTCON1 .................................................................... 89
INTCON2 .................................................................... 89
IPCx ............................................................................ 89
Initialization ............................................................... 126
Interrupt Disable ....................................................... 126
Interrupt Service Routine .......................................... 126
Trap Service Routine ................................................ 126
Disable...................................................................... 243
Initialization ............................................................... 243
Listen All Messages.................................................. 243
Listen Only................................................................ 243
Loopback .................................................................. 243
Normal Operation ..................................................... 243
Applicability................................................................. 65
Operation Example ..................................................... 64
Start and End Address ............................................... 64
W Address Register Selection .................................... 64
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