dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 198

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 13-2:
DS70291C-page 196
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-2
bit 1
bit 0
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, the TSIDL bit
TON
R/W-0
U-0
—
2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits
(2)
must be cleared to operate the 32-bit timer in Idle mode.
have no effect.
TON: Timery On bit
1 = Starts 16-bit Timer
0 = Stops 16-bit Timer
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1 = Discontinue timer operation when device enters Idle mode
0 = Continue timer operation in Idle mode
Unimplemented: Read as ‘0’
TGATE: Timer
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
TCKPS<1:0>: Timer
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
Unimplemented: Read as ‘0’
TCS: Timer
1 = External clock from TxCK pin
0 = Internal clock (F
Unimplemented: Read as ‘0’
TGATE
R/W-0
U-0
—
TyCON: TIMER CONTROL REGISTER (y = 3 or 5)
(2)
x
Clock Source Select bit
W = Writable bit
‘1’ = Bit is set
x
Gated Time Accumulation Enable bit
TSIDL
R/W-0
R/W-0
(2)
OSC
TCKPS<1:0>
x
x
x
Input Clock Prescale Select bits
(1)
/2)
(1)
R/W-0
U-0
(2)
Preliminary
—
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
(2)
(2)
U-0
U-0
—
—
© 2009 Microchip Technology Inc.
x = Bit is unknown
TCS
R/W-0
U-0
—
(2)
U-0
U-0
—
—
bit 8
bit 0