emc166sp16k Emlsi Inc., emc166sp16k Datasheet - Page 62

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emc166sp16k

Manufacturer Part Number
emc166sp16k
Description
1mx16 Bit Cellularram
Manufacturer
Emlsi Inc.
Datasheet
Figure 51. Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW
Note:
1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (t
interval. Otherwise, t
LB#/UB#
DQ[15:0]
IN/OUT
A[19:0]
ADV#
WAIT
WE#
OE#
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
CPH
High-Z
is only required after CE#-controlled WRITEs.
Valid Address
t
AS
t
CW
t
WP
Data
t
DH
t
WPH
t
WC
Valid Address
t
t
AW
BW
t
DW
Data
t
WR
High-Z
62
t
HZ
Note 1
t
CPH
V
V
OH
OL
t
BLZ
t
LZ
CPH
t
AA
) to schedule the appropriate refresh
Valid Address
t
OLZ
Don’t Care
t
OE
EMC166SP16K
1Mx16 CellularRAM
Valid Output
t
t
HZ
HZ
t
Undefined
BHZ
t
OHZ

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