emc166sp16k Emlsi Inc., emc166sp16k Datasheet - Page 6

• Manufacturer Part Number: emc166sp16k
• Description: 1mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

General Description
CellularRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications.
The 16Mb CellularRAM device has a DRAM core organized as 1 Meg x 16 bits. These devices include an industry-standard burst
mode Flash interface that dramatically increase read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offer-
ing.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self refresh mechanism. The hidden
refresh requires no additional support from the system memory controller and has no significant impact on device READ/WRITE per-
formance.
Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM
device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh con-
figuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded
with default settings during power-up and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. 16Mb CellularRAM products include three
mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit refresh to only that part of the DRAM
array that contains essential data. Temperature compensated refresh (TCR) uses an onchip sensor to adjust the refresh rate to match
the device temperature-the refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep
power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The
system configurable refresh mechanisms are accessed through the RCR.
This 16Mb CellularRAM devices is compliant with the industry-standard CellularRAM 1.5 feature set established by the CellularRAM
Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, additional wrap
options, and a device ID register (DIDR).
Figure 1 : Functional Block Diagram -1 meg x 16
Note: Functional block diagrams illustrate simplified device operation. See pin descriptions(Table 1); Bus operations table(Table 2); and timing diagrams
for detailed information.
ADV#
WAIT
WE#
CRE
OE#
CLK
CE#
UB#
LB#
A[19:0]
Control
Logic
Bus Configuration
Register (BCR)
Refresh Configuration
Register (RCR)
Device ID Register
(DIDR)
Address Decode
Logic
6
Internal
1,024K x 16
DRAM
MEMORY
ARRAY
External
Input
Output
MUX
and
Buffers
EMC166SP16K
1Mx16 CellularRAM
DQ[15:8]
DQ[7:0]