emc166sp16k Emlsi Inc., emc166sp16k Datasheet - Page 55

• Manufacturer Part Number: emc166sp16k
• Description: 1mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

Figure 44. Burst READ Interrupted by Burst READ or WRITE
Note:
1. Non-default BCR settings for burst READ interrupted by burst READ or WRITE: Fixed or variable latency code two (three clocks); WAIT active
2. Burst interrupt shown on first allowable clock (i.e., after the first data received by the controller).
3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than t
LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.
DQ[15:0] OUT
2nd Cycle READ
2nd Cycle READ
2nd Cycle READ
LB#/UB#
A[19:0]
ADV#
WAIT
WE#
CLK
OE#
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
IH
IL
OH
OL
t
t
Address
t
t
SP
SP
CSP
SP
Valid
t
t
t
HD
HD
HD
t
CLK
t
ACLK
t
BOE
DQ[15:0] IN
2nd Cycle Write
2nd Cycle Write
2nd Cycle Write
Output
Valid
LB#/UB#
t
CEW
t
t
Address
t
SP
SP
OE#
SP
Valid
t
t
t
HD
HD
t
HD
KHTL
t
OHZ
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
55
READ Burst interrupted with new READ or WRITE. See Note 2.
t
CEM
High-Z
High-Z
(Note 3)
t
BOE
t
Output
SP
CEM
Valid
D0
t
ACLK
t
.
HD
t
KOH
Output
Valid
D1
Output
Valid
D2
Don’t Care
EMC166SP16K
1Mx16 CellularRAM
Output
Valid
D3
t
HD
t
OHZ
High-Z
Undefined