emc166sp16k Emlsi Inc., emc166sp16k Datasheet - Page 32

• Manufacturer Part Number: emc166sp16k
• Description: 1mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

Table 15: Burst READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Note:
1. A refresh opportunity must be provided every t
2. The High-Z timings measure a 100mV transition from either V
3. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either V
Address access time (fixed latency)
ADV# access time (fixed latency)
Burst to READ access time (variable latency)
CLK to output delay
Address hold from ADV# HIGH(fixed latency)
Burst OE# LOW to output delay
CE# HIGH between subsequent burst or mixed mode
operations
Maximum CE# pulse width
CE# or ADV# LOW to WAIT valid
CLK period
Chip select access time (fixed latency)
CE# setup time to active CLK edge
Hold time from active CLK edge
Chip disable to DQ and WAIT High-Z output
CLK rise or fall time
CLK to WAIT valid
Output HOLD from CLK
CLK HIGH or LOW time
Output disable to DQ High-Z output
Output enable to Low-Z output
Setup time to active CLK edge
Parameter
HIGH, or b) CE# HIGH for longer than 15ns.
CEM
. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
Symbol
t
t
t
t
t
t
t
CBPH
t
t
t
t
AADV
t
t
KHKL
KHTL
t
ACLK
CEM
CEW
t
t
ABA
AVH
BOE
CSP
t
t
KOH
t
OHZ
t
OLZ
t
CLK
CO
HD
HZ
KP
SP
AA
OH
or V
Min
7.5
2.5
1.5
2
5
1
2
3
3
2
-
-
-
-
-
-
-
-
-
-
-
OL
133MHz
32
toward VccQ/2.
Max
35.5
5.5
7.5
1.2
5.5
70
70
20
70
4
7
7
-
-
-
-
-
-
-
-
-
9.62
Min
2
5
1
3
2
2
3
3
3
-
-
-
-
-
-
-
-
-
-
-
104MHz
OH
Max
35.9
7.5
1.6
70
70
20
70
or V
7
4
7
7
7
-
-
-
-
-
-
-
-
-
OL
.
EMC166SP16K
12.5
Min
2
6
1
4
2
2
4
3
3
1Mx16 CellularRAM
-
-
-
-
-
-
-
-
-
-
-
80MHZ
Max
7.5
1.8
70
70
46
20
70
9
4
7
9
7
-
-
-
-
-
-
-
-
-
Unit Note
ns
ns
ns
ns
ns
ns
ns
µ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
1
1
3
2
3