emc166sp16k Emlsi Inc., emc166sp16k Datasheet - Page 34

• Manufacturer Part Number: emc166sp16k
• Description: 1mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

Table 17: Burst WRITE Cycle Timing Requirements
Note:
1. t
2. A refresh opportunity must be provided every t
3. The High-Z timings measure a 100mV transition from either V
Address and ADV# LOW setup time
Address HOLD from ADV# HIGH(fixed latency)
CE# HIGH between subsequent burst or mixed mode
operations
Maximum CE# pulse width
CE# LOW to WAIT valid
Clock period
CE# setup to CLK active edge
Hold time from active CLK edge
Chip disable to WAIT High-Z output
CLK rise or fall time
Clock to WAIT valid
CLK HIGH or LOW time
Setup time to activate CLK edge
Parameter
HIGH, or b) CE# HIGH for longer than 15ns.
AS
required if t
CSP
> 20ns.
CEM
. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
Symbol
t
t
t
t
t
t
CBPH
t
t
KHKL
KHTL
CEW
CEM
CSP
t
t
AVH
CLK
t
t
t
AS
HD
HZ
KP
SP
OH
or V
Min
7.5
2.5
1.5
0
2
5
1
3
2
-
-
-
-
OL
133MHz
34
toward VccQ/2.
Max
7.5
1.2
5.5
4
7
-
-
-
-
-
-
-
-
9.62
Min
0
2
5
1
3
2
3
3
-
-
-
-
104MHz
Max
7.5
1.6
4
7
7
-
-
-
-
-
-
-
-
EMC166SP16K
12.5
Min
0
2
6
1
4
2
4
3
1Mx16 CellularRAM
-
-
-
80MHZ
Max
7.5
1.8
4
7
9
-
-
-
-
-
-
-
-
Unit Notes
µ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
1
2
2
3