W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 76

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW#
trailing edge of IOW# latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read
cycle to be performed and the data to be output to the host CPU.
6.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
When accesses are made to any EPP data port, the contents of DB0-DB7 are b uffered (non-inverting)
and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP
data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the
EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of
cycle to be performed and the data to be output to the host CPU.
6.2.6 Bit Map of Parallel Port and EPP Registers
Data Port (R/W)
Status Buffer (Read)
Control Swapper
(Read)
Control Latch (Write)
EPP Address Port R/W)
EPP D ata Port 0 (R/W)
EPP Data Port 1 (R/W)
EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
REGISTER
BUSY#
PD7
PD7
PD7
PD7
PD7
PD7
7
1
1
ACK#
7
PD6
PD6
PD6
PD6
PD6
PD6
6
1
1
6
c
auses an EPP address write cycle to be performed, and the
5
PD5
PD5
PD5
PD5
PD5
PD5
DIR
PE
5
1
4
- 67 -
IRQEN
3
SLCT
PD4
PD4
PD4
PD4
PD4
PD4
IRQ
4
2
1
ERROF#
SLIN
SLIN
PD3
PD3
PD3
PD3
PD3
PD3
3
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Publication Release Date: Feb. 2002
INIT#
INIT#
PD2
PD2
PD2
PD2
PD2
PD2
2
1
IOR#
W83697HF/F
AUTOFD#
AUTOFD#
causes an EPP read
PD1
PD1
PD1
PD1
PD1
PD1
1
1
Revision 0.70
STROBE#
STROBE#
TMOUT
PD0
PD0
PD0
PD0
PD0
PD0
0