W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 157

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

CR62, CR 63 (Default 0x00, 0x00)
CRF0 (GP10-GP17 I/O selection register. Default 0xFF)
CRF1 (GP10-GP17 data register. Default 0x00)
CRF2 (GP10-GP17 inversion register. Default 0x00)
10.11
CR30 (MIDI Port Default 0x00)
CR60, CR 61 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise)
CR62, CR 63 (Default 0x00, 0x00 )
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
When set to a '1', respective GPIO port is programmed as an input port.
If a port is programmed to be an output port, then its respective bit can be read/written
When set to a '0', respective GPIO port is programmed as an output port.
If a port is programmed to be an input port, then its respective bit can only be read.
These two registers select the GPIO1 base address [0x100:0xFFF] on 1 byte boundary
These two registers select the MIDI Port base address [0x100:0xFFF] on 2byte boundary.
These two registers select the GPIO5 base address [0x100:0xFFF] on 4byte boundary.
IO address + 2 : CRF4 base address
IO address : CRF1 base address
IO address :
IO address + 1 : CRF3 base address
IO address + 3 : CRF5 base address
Bit 7 - 1 : Reserved.
Bit 0
Logical Device 8 (MIDI Port and GPIO Port 5)
= 1
= 0
MIDI/GP5 port is Activate
MIDI/GP5 port is inactive.
CRF1 base address
- 148 -
Publication Release Date: Feb. 2002
W83697HF/F
Revision 0.70