W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 61

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

4.2.5
This register is used to control the FIFO functions of the UART.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the
TABLE 4-3 FIFO TRIGGER LEVEL
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
BIT 7
interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver
FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
0
0
1
1
UFR bit 0 = 1.
logical 0 by itself after being set to a logical 1.
logical 0 by itself after being set to a logical 1.
other bits of UFR are programmed.
UART FIFO Control Register (UFR) (Write only)
BIT 6
0
1
0
1
7
6
5
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
4
3
2
1
- 52 -
0
01
04
08
14
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Publication Release Date: Feb. 2002
W83697HF/F
Revision 0.70