W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 54

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

DSKCHG (Bit 7):
This bit indicates the status of DSKCHG# input.
Bit
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
3.2.9
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no precompensation. It has no function and can be set by software.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
6 -4: These bits are always a logic 1 during a read.
Configuration Control Register (CC Register) (Write base address + 7)
x
7
X
x
7
6
X
6
x
5
5
X
x
4
X
4
X
X: Reserved
3
- 45 -
x
3
2
x
X
2
:
1
Reserved
1
0
0
DRATE0
DRATE1
NOPREC
Publication Release Date: Feb. 2002
DRATE0
DRATE1
W83697HF/F
Revision 0.70