W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 49

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

3.2.6
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the
FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by
the DR REGISTER. The real data rate is determined by the most recent write to either of the DR
REGISTER or CC REGISTER.
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0
1
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for the combination of these bits.
FDC in normal mode
FDC in power-down mode
Data Rate Register (DR Register) (Write base address + 4)
2
0
0
0
0
1
1
1
1
PRECOMP
1
0
0
0
1
0
1
1
1
0
0
1
0
0
1
0
1
1
7
6
5
0
0.00 nS (disabled)
Default Delays
250K - 1 Mbps
4
125.00 nS
166.67 nS
208.33 nS
250.00 nS
41.67 nS
83.34 nS
3
- 40 -
PRECOMPENSATION DELAY
2
1
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
Publication Release Date: Feb. 2002
2 Mbps Tape drive
0.00 nS (disabled)
Default Delays
125.00 nS
41.17 nS
104.2 nS
20.8 nS
83.3 nS
62.5nS
W83697HF/F
Revision 0.70